About
The FOSSi Foundation is proud to announce Latch-Up, a conference dedicated to free and open source silicon to be held over the weekend of May 4th and 5th in Portland, Oregon, USA.
Latch-Up is a weekend of presentations and networking for the open source digital design community, much like its European sister conference ORConf.
Latch-Up in Portland is now over. the FOSSi Foundation would like to extend a massive thank you to all presenters, participants, and sponsors of the event.
Plenty of photos of the action can be found on the @LatchUpConf twitter feed. Find the group photo here - thanks to >Monica Houston of Hackster.io!
Videos of the event are becoming available on the Latch-Up 2019 playlist on the FOSSi Foundation's YouTube channel.
Questions? Ping the organizers via @LatchUpConf or email.
Registration
We're sorry to say that Latch-Up is fully subscribed and registration is now closed.
We ask all Latch-Up participants to adhere to the the FOSSi Foundation code of conduct throughout the event.
Professional Tickets
Attendees who are joining us at Latch-Up on behalf of their company and/or can claim the conference as professional training expense are encouraged to purchase a professional ticket. These ticket sales help us provide all that we do at Latch-Up and keep the event accessible to all members of the community.
Professional tickets are £500 (+sales tax if applicable) and can by bought here via the PayPal button below or by email.
Submit a talk
Latch-Up is no longer open for talk submissions. If you'd like to submit a lightning talk, do so here: https://forms.gle/g6BcnTSmrS22Znzu6.
Sponsorship and Volunteering at Latch-Up
Latch-Up is free to attend, but we aim to provide catering and the like during the event. Latch-Up is also a great way to get your company or brand in front of lots of engineers and hackers on the day, and thousands more through recordings of the event. So please get in touch if you'd like to explore sponsorship opportunities.
Latch-Up is organized by volunteers on behalf of the FOSSi Foundation. We are currently looking for more people to help out with arrangements and putting on the event, so please do email us if you would like to voltuneer for during the event with setup, AV, or even just local knowledge so we can plan the weekend better.
Venue
We are pleased to announce that Latch-Up 2019 will be held in the "101" space of Portland's Revolution Hall. The venue's address is 1300 SE Stark St, Portland, OR 97214
Sponsors
Donate
You can also support us with small donations via Paypal:
Conference Dinner
A dinner will be arranged for the Saturday evening of the conference, as is tradition at our sister event, ORConf. All attendees are encouraged to join us for a relaxed dinner and a few drinks after Saturday's proceedings.
We're pleased to announced that the fantastic folks at SiFive are the sponsors of this year's conference dinner.
The dinner will be held at Rock Bottom Brewery (map).
Patch-Up at Latch-Up: Tim Videos Hackfest
On Friday May 3rd, prior to the weekend of Latch-Up, we will host a hackfest for Tim Videos, a live video recording project built entirely out of open source hardware, gateware and software.
This will be suitable for users, developers and anyone curious about getting involved with the Tim Videos project. Helping out on the day will be the man himself, Tim Ansell and Carl Karsten of Next Day Video.
The day will center around hacking on litex-buildenv with a focus on the HDMI2USB firmware. The litex-buildenv project is an SoC with 3 architectural flavours of micrprocessor to choose from; LM32 (lm32), RISC-V (3 implementations!) and OpenRISC 1000 (mor1kx). As for software, you can run code bare metal, in micropython, and on OSes such as Zephyr and Linux. The system builds with open source FPGA tools and runs on iCE40 FPGAs. In addition, Tim will have Fomu hardware to disseminate, and Opsis and NeTV2 hardware for people to hack on.
For more info on the project, check these videos out: 1, 2.
So if you're proficient (or near enough!) in HDLs, software, and debugging embedded systems and would like to get involved, or exposed to some new tools, then come on down! Or even if you just want to drop by and say hi and look over people's shoulders, that's fine too.
Where and when
The event will run from 2 - 8PM, Friday May 3rd at CTRL-H (^H) / the PDX Hackerspace, 7608 N Interstate Ave, Portland, OR 97217. Bring your laptop, any suitable hardware and a willingess to get your hands "dirty" on an active open source video hardware project. A dinner barbecue will be put on by the fine folks at ^H.
Register
In order to help us plan the day, we ask that you register that you're intending to come - even if you're just coming to hang out. Please fill in this short form to register. This isn't necessary, please do turn up even if you haven't registered, but it does help us.
A big thanks to ^H / PDX Hackerspace for hosting and sponsoring Patch-Up at Latch-Up: Tim Videos Hackfest
More about Latch-Up
Technically speaking, latch-up is a short circuit, an inadvertent path of low-impedance. We have co-opted this word to represent what we’d like to encourage among members of the community: paths of communication leading to collaboration, inadvertent or not.
Latch-Up 2019 in Portland opens a new chapter for the FOSSi Foundation, with it being the first event in the spirit of ORConf held in North America. Latch-Up is a community-focused conference for open source semiconductor, digital design and embedded systems professionals and enthusiasts. Expect presentations on a wide range of topics; open source IP blocks and SoCs, open source simulators, compilers, synthesis and physical implementation tools for both FPGA and ASIC.
Latch-Up aims to bring together the North American open source digital design community for an event in the mould of ORConf - the FOSSi Foundation’s annual European community conference. Like ORConf, Latch-Up will be will be free to attend and consist of a relaxed format of presentations and discussions throughout a weekend, with plenty of time for networking. A dinner on the Saturday evening will be arranged and all attendees are invited to attend.
These events go to the FOSSi Foundation's goal of lowering barriers of entry to the digital design field, whilst encouraging the open source development model and promoting open collaboration.
We recognise the keen interest in this area in the Americas and this year are putting effort into organizing an event which will encourage wider awareness amongst enthusiasts of the projects that we’ve been hearing about at ORConf since 2012.
Don't forget to follow @LatchUpConf or email us/DM us if you have any questions.
Schedule
Saturday
Sunday
| 09:00 | Registration open | |
| 09:30 | (20/10) | BaseJump STL: a Standard Template Library for Hardware Design by Daniel Petrisko |
| 10:00 | (20/10) | OSVVM, VHDL's #1 FPGA Verification Library by Jim Lewis |
| 10:30 | (20/10) | Verifying Open-Source Silicon with SystemVerilog: Getting in on the Ground Floor by Matthew Ballance |
| 11:00 | (20) | Break |
| 11:20 | (15/5) | RISC-V in Debian by Vagrant Cascadian |
| 11:40 | (30) | Lightning Talks |
| 12:10 | (1h10) | Lunch |
| 13:20 | (20/10) | FuseSoC - Cores have never been so much fun by Olof Kindgren |
| 13:50 | (20/10) | DUH: document and tools for HW design reuse by Aliaksei Chapyzhenka |
| 14:20 | (20/10) | Nyuzi: An Open Source GPGPU Processor by Jeff Bush |
| 14:50 | (20) | Break |
| 15:10 | (20/10) | OpenRAM: An Open Source Memory Compiler by Matthew Guthaus |
| 15:40 | (20/10) | SYZYGY: An Open Standard For Semiconductor Evaluation by Tom McLeod |
| 16:00 | (20) | Open-Source FPGA tools, how and why? by Piotr Esden-Tempski |
| 16:30 | Close |
Key: (20/10) - presentation with 20 minutes + 10 minutes Q&A
Presentations
Emulation of vintage integrated circuits through die analysis and reverse-EDA
Despite being sold in the millions, video games based on discrete game ICs have had minimal emulation developed. This is primarily due to the circuitry being a literal "black box" as only the manufacturer possessed the designs. In addition, much of the documentation surrounding these games has disappeared over the years.
Cole has been developing a process to re-implement these stubborn circuits in modern FPGAs as well as software. It involves extracting a transistor-level netlist from high-resolution photographs of the exposed silicon die. Reverse-engineering and slow simulation is achieved using tools pioneered by the visual6502 project. This is followed by reverse-EDA performed by custom tools being developed. The transistor-level design is automatically converted into a more abstract RTL circuit description.
Verilog obtained from the above process will be ported to the tinyFPGA board, the MiSTer hardware emulation project, and the MAME software emulator. The intermediate files will be open-source in the spirit of the target projects.
Presenter: Cole Johnson
Cole has only recently joined hardware design circles as a result of his reverse-engineering project, which began over two years ago. He looks forward to potential work on RISC-V and ASIC design in the future.
How I started learning FPGA: My journey writing a GameBoy in Verilog
Coding can be fun, there are many people coding in their free time just for fun. FPGA's unique features and capabilities makes it an attractive target for enthusiasms. VerilogBoy is such an FPGA project, that is built simply for fun. The VerilogBoy project consists of two parts. The first part is implementing a GameBoy compatible machine in Verilog. The second part is building an FPGA-based handheld game console.
This presentation will run through the process of the creation of the project, share some of the experience along the way, also provide some future prospects of the project.
Presenter: Wenting Zhang
Wenting Zhang is a undergraduate student of Computer Science and Electrical Engineer major, who has just started learning digital logic 1 year ago. He has built several open source projects such as E-Ink software timing controller and LCD scan doubler before. He is trying to learn more and get more involved in both open source community and semiconductor industry.
Diagrams and system visualisation in chip design
Chip designers use multiple forms of illustrations to present information of technical nature quickly and clearly. Illustrations employed to mobilize human visual system ability to recognize trends, patterns and differences. Some forms of illustrations are universally accepted. Data tables, plots, line charts, mechanical drawings can be used to communicate information to the general public. Specialized diagram types (like UML) can be reused from software or system design practice. Such diagrams are capable of describing complex structure or behavior and convey this information to the broad science and engineering community.
Like any other specific field of science / engineering -- chip designers developed own specialized visual language to communicate complex ideas with clarity, precision and efficiency. Schematic symbols; timing, circuit, layout diagrams were originally developed for paper medium, now migrated into electronic documentation. Many design tools exists to create illustrations and diagrams. From generic to specialized. Some require freehand drawing skills, some perform automatic layout.
This talk is about ideas, principles and tools that would help you to create good diagrams.
Presenter: Aliaksei Chapyzhenka
Aliaksei Chapyzhenka is an engineer at SiFive Inc., author of the WaveDrom project and OSS contributor since 2011.
OSVVM, VHDL's #1 FPGA Verification Library
Open Source VHDL Verification Methodology (OSVVM) is an ASIC level VHDL verification methodology that is simple enough to use even on small FPGA projects. OSVVM offers the same capabilities as other verification languages such as SystemVerilog and UVM.
This presentation provides an overview of OSVVM's capabilities, including:
OSVVM is implemented as a library of free, open-source packages. It uses these packages to create features that rival language based implementations in both conciseness, simplicity, and capability.
In exciting news, The 2018 Wilson Research Group ASIC and FPGA Functional Verification Study, which is sponsored by one of the EDA vendors revealed that OSVVM is the number 1 VHDL FPGA verification library.
Looking to improve your VHDL FPGA verification methodology? OSVVM provides a complete solution for VHDL ASIC or FPGA verification. There is no new language to learn. It is simple, powerful, and concise. Each piece can be used separately. Hence, you can learn and adopt pieces as you need them."
Presenter: Jim Lewis
Jim Lewis has over 30+ years of design, teaching, and problem solving experience and is well known within the VHDL community. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, IMA E1/T1 networking, fighter jets, video phones, and space craft.
Live Graph infrastructure for Synthesis and Simulation
LGraph is compiler infrastructure to support hardware languages. The goal is to become the LLVM of hardware. LGraph is a graph optimized for live synthesis and simulation (Live Synthesizes Graph or LGraph for short). By live, we mean that small changes in the design should have results in few seconds. The goal is that any code change can have its synthesis and simulation setup ready under 30 seconds with a goal of under 4 seconds in most cases.
Presenter: Jose Renau
Jose is the lead designer coordinating several students at UCSC on LGraph
SYZYGY: An Open Standard For Semiconductor Evaluation
So you've designed and built an amazing new piece of silicon. No doubt customers are lining up to try it out, but how do you go about providing an evaluation platform for them?
SYZYGY provides the answer with an open standard for high performance connectivity to an FPGA. SYZYGY was designed to economize FPGA pin usage without compromising per-pin performance. Built with a focus on FPGA-specific requirements, SYZYGY fits comfortably between Digilent Pmod and VITA-57 FMC standards. Developing a SYZYGY-based evaluation peripheral opens up support for numerous host platforms as well as easier integration into your customer's product. This presentation will provide an overview on the SYZYGY standard, why it's needed, and what it offers.
Presenter: Tom McLeod
Tom McLeod is a design engineer at Opal Kelly Inc., the publishers of the SYZYGY specification. He was a member of the group that wrote the SYZYGY specification and has participated in the design of a number of products implementing the specification.
FuseSoC - Cores have never been so much fun
In many ways, HDL developers have been many years behind their counterparts in the software world. One such area is core management. Where the software developers simply specify which libraries they depend on, HDL developers rely on copying around source code. Where software developers can select their build tool with a flick of a switch, HDL developers use tool-specific project files powered by custom makefiles.
FuseSoC rectifies this by bringing a modern package manager and a uniform build system to HDL developers, making it easy to reuse existing code, change tools and move projects between FPGAs from different vendors. Having been around for seven years there are now hundreds of FuseSoC-compatible cores and 14 different simulation, synthesis and lint tools supported. This presentation will give an overview of where FuseSoC can help spending less time on the cores, and more time on the core business
Presenter: Olof Kindgren
Olof is a senior digital design engineer working for Qamcom Research & Technology. He became actively involved with free and open source silicon through the OpenRISC project in 2011 and has since then worked on many FOSSi projects with a special interest in tools and collaborations.
Notable work include the FuseSoc IP core package manager; SERV, the award-winning RISC-V CPU and ipyxact, the IP-XACT Python library. In 2015, he also co-founded FOSSi Foundation, a vendor-independent organization with the mission to promote and assist Open Source Silicon in academia, the industry and for hobbyists alike.
Lessons learned customising the Rocket RISC-V core
This presentation will cover Morse Micro's adaptation of the Berkeley/SiFive Rocket chip generator in developing single-chip 802.11ah solutions. We will discuss the pros and cons of Chisel, Rocket's architecture, and aspects of our work in taking the Rocket project and implementing multiple deeply-embedded-class micro-controllers.
Presenter: Julius Baxter
Julius has a decade of open source hardware experience through his involvement with the OpenRISC project and later the FOSSi Foundation. Aside from evangelizing for open source digital design, he works as a digital design engineer on mixed signal wireless chips.
Netlistsvg: How to Draw a Better Schematic than Graphviz
Taking a description of components and the connections between them and converting it into a reasonable looking image is a surprisingly complicated problem. Digital netlist visualization is useful for pedagogy, documentation, and debugging and is commonly integrated into proprietary FPGA toolchains such as Vivado or Quartus. Netlistsvg is a simple tool that takes yosys netlists in JSON format, and attempts to create an easily understandable image in SVG format.
Presenter: Neil Turley
Neil is a Software Engineer at National Instruments on the CompactRIO team. Netlistsvg has been a personal project of his for a few years.
OpenRAM: An Open Source Memory Compiler
OpenRAM is an open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technology.
Presenter: Matthew Guthaus
Matthew Guthaus is a Professor at the University of California Santa Cruz in the Computer Science and Engineering department. His research interests are in low-power computing and computer-aided design. This includes new circuits, architectures, and software to address integration in modern design flows.
Verifying Open-Source Silicon with SystemVerilog: Getting in on the Ground Floor
Open source and industry have a long history of overlapping in the software space. Engineers from industry often work on open-source software in their free time, open source software is used in commercial applications, and students use open-source software to learn about how real software is designed, developed, and tested. A key enabler is that open-source software is largely developed and tested in the same way that commercial software is. Commercial software development often uses commercial tools with features beyond what is available to open-source developers, but the large degree to which techniques and methodologies are aligned facilitates collaboration.
What of open source silicon? We certainly use standard design languages (Verilog and VHDL). But verification in the industry is typically done with SystemVerilog and UVM, and SystemVerilog tools are out-of-reach for the open-source silicon developer. Or, are they? As it turns out, there are both open-source and freely-available tools, and educational resources, to help open-source silicon developers create verification environments that align with commercial verification practices. This talk will present tools and educational resources for creating SystemVerilog and UVM testbench environments, as well as techniques for creating SystemVerilog and UVM testbenches for open-source silicon that both work with freely-available tools and scale to take advantage of the features of commercial simulation tools.
Presenter: Matthew Ballance
Matthew Ballance is a Product Engineer at Mentor, A Siemens Business working with Portable Stimulus. Over the past 20 years in the EDA industry, he has worked in product development, marketing, and management roles in the areas of hardware/software co-verification, transaction-level modeling, IP encapsulation and reuse, and Portable Test and Stimulus. Nights and weekends, Matthew works on open-source hardware and software projects.
RISC-V in Debian
Debian's port for 64-bit RISC-V, riscv64, already builds 88% of Debian's available packages. It's possible to build a foreign-architecture chroot with qemu, or a fully virtualized riscv64 system. What are the remaining blockers to include riscv64 in a Debian release?
Presenter: Vagrant Cascadian
Vagrant Cascadian is a Debian developer since 2010 and maintains packages in Debian such as U-boot and arm-trusted-firmware, as well as maintaining a build farm for the Reproducible Builds project of 24 boards in under 300 watts. A RISC-V cheerleader and enthusiast, looking forward to a future with auditable hardware.
DVKit: An Integrated Development Environment for Design and Verification Engineers
Design and Verification engineers develop code using a plethora of languages -- Verilog, SystemVerilog, C/C++, Python, Perl, etc. Whether developing commercial or open source IP, reuse is critical, which means that DV engineers need to efficiently comprehend and work with code written by others. DVKit is an Eclipse-based Integrated Development Environment (IDE) that supports developing in a wide variety of software and hardware description languages much more efficiently than can be done with a text editor.
This talk will introduce you to the differences between a text editor and an IDE. We will look at features of DVKit that boost productivity on any type of text file, and focus on features that make navigating and developing SystemVerilog and Verilog designs and testbench environments more efficient and effective.
Presenter: Matthew Ballance
Nyuzi: An Open Source GPGPU Processor
Nyuzi began as a way to explore tradeoffs between general purpose and fixed function hardware. This presentation will talk about the original goals of the project, the process of building a new microarchitecture, and some learnings from it.
Presenter: Jeff Bush
Jeff Bush has spent most of his professional career building software for consumer electronics products. Nyuzi is a personal project.
OpenPiton+Ariane: Making Ariane Multicore with OpenPiton’s P-Mesh
You may have heard of Ariane from ETH Zurich, or of OpenPiton from Princeton University, but now from the makers of both, comes OpenPiton+Ariane!
By modifying the Ariane RISC-V (RV64GC) core’s L1 cache interface to support the P-Mesh cache-coherence protocol, we replaced OpenPiton’s original OpenSPARC T1 core and then enhanced P-Mesh to support RISC-V atomic operations.
Since bringing up SMP Linux on FPGA, OpenPiton+Ariane is the first open-source, Linux-booting, RISC-V system that scales from single-core to manycore. OpenPiton+Ariane inherits all of the capabilities of OpenPiton and of Ariane, bringing them together in a single scalable, configurable, and easy-to-use platform ideal for rapid prototyping. This is all available under permissive licences from our GitHub repositories.
Presenter: Jonathan Balkind
Jonathan Balkind is a sixth year PhD Candidate at Princeton University, working with David Wentzlaff. He has led the development of OpenPiton since its first release in 2015 and has given ten tutorials at universities and conferences worldwide. His research currently focuses on open-source hardware and Function-as-a-Service Serverless Computing.
JuxtaPiton: The First Open-Source, Heterogeneous-ISA Processor
Heterogeneous-ISA processors have become a topic of research interest due to the increasing need for energy efficiency. Without a fully open-source implementation of a heterogeneous-ISA processor, it is difficult to test full-stack modifications. By connecting PicoRV32 to the OpenPiton cache system, we created JuxtaPiton, a heterogeneous-ISA platform with both OpenPiton’s original OpenSPARC T1 cores and PicoRV32 cores.
This project was the first time a new core was integrated into OpenPiton, so I will describe the process I developed to integrate PicoRV32 and which has since been used to connect five other cores to OpenPiton. I will also describe the runtime system we use to offload binaries from Linux on the SPARC core to the bare-metal environment on PicoRV32 core and to proxy syscalls from the running binary.
Presenter: Katie Lim
Katie Lim is a first-year PhD student at University of Washington working with Michael Taylor and Tom Anderson. During her undergrad at Princeton University, she contributed to OpenPiton, created JuxtaPiton as her senior thesis project, and interned at lowRISC. Her research interests are in abstractions for heterogeneous architectures.
FireSim: Open-Source Easy-to-use FPGA-Accelerated Cycle-Exact Hardware Simulation in the Cloud
We present FireSim , an easy-to-use, open-source, FPGA-accelerated cycle-accurate hardware simulation platform that runs on Amazon EC2 F1. FireSim automatically transforms and instruments open-hardware designs (e.g. RISC-V Rocket Chip, BOOM, Hwacha, NVDLA, etc.) with the MIDAS framework into fast (10s-100s MHz), deterministic, FPGA-based simulators that enable productive pre-silicon verification and performance validation.
To model I/O, FireSim includes synthesizeable and timing-accurate models for standard interfaces like DRAM, Ethernet, UART, and others. By providing a framework to automate the management of FPGA infrastructure, FireSim also lets software developers get a head-start on building software for a novel hardware design, by letting these developers interact with the pre-silicon hardware design as they would a virtual machine. In effect, both hardware and software developers work from a single source of truth: the RTL for the hardware design.
Originally developed to simulate new datacenter architectures, FireSim is capable of scaling to simulating thousands of multi-core compute nodes, with an optional cycle-accurate network simulation tying them together. Leveraging AWS EC2 F1, FireSim removes the high capex traditionally involved in large-scale FPGA-based simulation, democratizing access to realistic pre-silicon hardware modeling of new designs. For designs that contain RISC-V SoCs, FireSim also provides compatible Linux distributions (Buildroot, Fedora) and automates the process of building complex workloads on top of these Linux distributions. By harnessing a standardized host platform and providing a large amount of automation/tooling, FireSim drastically simplifies the process of building and deploying large-scale FPGA-based hardware simulations.
In this talk, we cover the open-source FireSim framework, explore how users can use and modify the existing designs available in FireSim, and show how users can integrate and measure their own hardware designs.
Presenter: David Biancolin, Alon Amid
David Biancolin is a fifth-year Ph.D. student in the Berkeley Architecture Research (BAR) Group, part of the ADEPT lab at UC Berkeley, where he is co-advised by Jonathan Bachrach and Krste Asanovic. David received his BASc. in Engineering Science in the Electrical and Computer Engineering Option at the University of Toronto in 2014 (1T3 + PEY). David is a developer of FireSim and maintainer of MIDAS.
Alon Amid is a Ph.D. student in the Electrical Engineering and Computer Sciences department in UC Berkeley, advised by Borivoje Nikolic and Krste Asanovic. His research focus is in full-system co-design and evaluation of data-parallel architectures and large-scale distributed systems. Alon is a contributor to the FireSim project for FPGA-accelerated scalable cycle-accurate simulation, as well as a contributor to the RISC-V based chip-prototyping efforts at UC Berkeley.
The fusion of high-level synthesis with event-oriented hardware description
Many of the high-level synthesis (HLS) approaches take existing procedural programming languages, such as the C programming language, and add extensions to the language (e.g. pragmas) to accommodate high-level synthesis. An alternate approach is to use the myhdl design patterns to describe HLS chunks and integrate them with existing event-oriented (simulation-oriented, a.k.a RTL) hardware description languages (HDL). This approach allows a designer to seamlessly move between HDL and HLS levels of abstractions and use both descriptions in a single programming environment.
Presenter: Christopher Felton
Christopher L. Felton is a senior design engineer at the Mayo Clinic, a myhdl user and contributor since 2005.
The Berkeley-Out-of-Order-Machine: An Open Source Synthesizable High-Performance RISC-V Processor
We present BOOM, the Berkeley Out-of-Order Machine, a synthesizable and parameterizable open source RV64GC RISC-V processor written in the Chisel hardware construction language. BOOM is able to run Linux, Fedora, and other workloads both in the cloud using the FireSim FPGA simulation platform and on a taped-out academic chip. For researchers, BOOM serves as a highly productive platform for implementing and evaluating new high performance designs and accelerators.
In this talk, we briefly cover BOOM, and some of its features that make it amenable to research and integration with other projects. We discuss integration with the FireSim, results from hardware security research tackling Spectre-like vulnerabilities, and opportunities for specialization with custom accelerators.
Presenters: Jerry Zhao, Abe Gonzalez and Ben Korpan
Jerry is a zeroth-year Ph.D. student in the Berkeley Architecture Research (BAR) group, part of the ADEPT lab, advised by Krste Asanovic. Jerry is a developer of BOOM, and has contributed to other open-source hardware projects, including Hwacha and FireSim.
Abraham is a first-year Ph.D student in the ADEPT Lab at UC Berkeley. His research interests are in warehouse-scale computing and high performance microarchitectures. He currently works on the BOOM project and the FireSim project for research. Abraham received a B.S. in Electrical and Computer Engineering from the University of Texas at Austin in 2018.
Ben is a first-year Ph.D student in the ADEPT Lab at UC Berkeley, advised by Krste Asanovic. His research interests are in high performance microarchitectures. Ben received a B.A.Sc in Electronics Engineering from Simon Fraser University in 2018.
Higher-Order Hardware Design with Chisel 3
Chisel 3 is a hardware construction language embedded in Scala that enables digital designers to write parameterized generators using object-oriented and functional programming abstractions. The power of Chisel is not the language itself, but rather the abstractions one can create to make hardware design more productive, more reusable, and less error-prone. Sophisticated hardware generators like Rocket-Chip, BOOM, Hwacha, and even the Google Edge TPU are implemented using Chisel.
One of the most common challenges for new users is bridging the gap between toy examples and these complex, powerful generators. This talk is an attempt to help build that bridge. Let's use higher-level abstractions and higher-order programming to build better, reusable hardware.
Presenter: Jack Koenig
Jack became involved in the Chisel project as a graduate student at UC Berkeley. He is now a software engineer at SiFive and a maintainer of the Chisel3 and FIRRTL projects. His interests include hardware design, simulation, and programming languages.
DUH: document and tools for HW design reuse
SoC integration is a complex process requiring integration of multiple design components together. Typical “reusable” Soft / Hard core component comes with the intricate integration story hopefully described in some human readable User Guide document. Connecting all ports, parameters, registers, bus interfaces, clocks, resets, sideband signals, etc. becoming a very tedious, error prone process. Multiple attempts were made to introduce some sort of standard metadata exchange format to express this integration intent. Most of these formats are proprietary or EDA vendor specific and are semi-useful in the world of open source silicon tools.
DUH defines a JSON5-based document format and provides a suite of tools for handling reusable hardware components. Import tools allow extraction of ports, parameters, and other important integration information from available sources like Verilog, IP-XACT, SystemRDL, etc. Inference tools helps to reason about structure of the ports, standard bus interfaces, clocks, resets. Validation tools helps document author to maintain complete and consistent DUH document describing specific hardware component. Integration tools can read DUH documents to understand and satisfy an integration needs of these components.
Presenter: Aliaksei Chapyzhenka
BaseJump STL: a Standard Template Library for Hardware Design
SystemVerilog is widely used for hardware design in both academia and industry. BaseJump STL is an open-source Standard Template Library for synthesizable SystemVerilog that sharply reduces the time required to design digital circuits. This talk will overview the principles that underly the design of the BaseJump STL, including light-weight latency-insensitive interfaces that yield fast microarchitectures and low bug density; thin handshaking rules; fast porting of hardened chip regions across nodes; pervasive parameterization and specialization, and static error checking.
We then suggest extensions to SystemVerilog to make it a more functional design language, and briefly discuss validation of BaseJump STL through its use in past and ongoing projects.
Presenter: Daniel Petrisko
Daniel Petrisko is a PhD student at the Paul G. Allen School of Computer Science and Engineering at the University of Washington, working with Professors Michael Taylor and Mark Oskin. His research interests focus on accelerating hardware design through open-source software engineering principles.
Lessons Learned from Open-Sourcing NVDLA
In 2017, NVIDIA released their formerly-proprietary "NVDLA" deep learning accelerator IP as open source hardware. The process of transitioning from a closed IP model, backed by all the tooling available at a large company, to a community-available IP with the intent of being built "outside the walls" of NVIDIA, was unsurprisingly challenging, and the logistics of packaging hardware up for outside distribution modification was more difficult than we had originally anticipated.
In this discussion, I will talk some about things that went well, and things that I wish we had been prepared for at the start; additionally, I'll provide some tips and tricks for other organizations that may be interested in releasing their own IP as open source.
Presenter: Joshua Wise
Joshua is Senior Engineer and Vice President of Accelerated Tech, Inc, where he looks forward to helping you build high-quality hardware and software solutions to meet your low-level system design problems.
Previously, he was an ASIC architect at NVIDIA, working on -- among other things -- the image signal processor subsystem on Tegra, and the open-source effort for NVDLA.
Open-Source FPGA tools, how and why?
In this talk Piotr presents the OpenSource FPGA tool stack. Which devices are currently supported and which ones are being worked on. Also he talks about how these tools revived his interest in FPGA in general, and why they are important.
Presenter: Piotr Esden-Tempski
Piotr Esden-Tempski, is the founder of 1BitSquared and longtime Embedded Systems Engineer and hardware developer with an extensive history developing Open-Source and Open-Hardware Systems. He has a long history developing and manufacturing UAV autopilot hardware for the Paparazzi UAV framework, manufacturer of the 1Bitsy ARM development platform, the Black Magic Probe JTAG/SWD programmer/debugger hardware and the iCEBreaker FPGA development and teaching platform. Piotr is passionate about introducing new people to embedded hardware development using open-source tools and solutions that can also be used by professionals for production applications!